Serial Peripheral Interface Registers
A-56 ADSP-21368 SHARC Processor Hardware Reference
SPI Port Status (SPISTAT, SPISTATB) Registers
These registers’ addresses are 0x1002 and 0x2802 (SPISTATB). The reset
value for these registers is 0x01.The SPISTAT and SPISTATB registers,
shown in Figure A-24 and described in Table A-11, are read-only registers
used to detect when an SPI transfer is complete, if transmission/reception
errors occur, and the status of the TXSPI and RXSPI FIFOs. The bits in
these registers are W1C-type (write 1-to-clear).
20 ILPBK Internal Loop Back.
0 = No internal loopback
1 = Internal loopback enabled
31–21 Reserved
Figure A-24. SPISTAT, SPISTATB Registers
Table A-10. SPICTL Register Bit Descriptions (Cont’d)
Bit Name Description
31 30 29 28 27 26 24 23 22 21 20 19 18 17 16
0000000000000000
Reserved
15 14 13 12 11 10 8 7 6 5 4 3 2 1 0
0000000000000000
Reserved
TXCOL
SPIF
SPI Transmit Transfer
Complete
1=Transfer complete
0=Transfer active
MME
Multimaster Error
1=SPIDS
asserted by slave
0=No error
Transmit collision error
RXS
TXSPI Data Buffer Status (Read-Only)
1=Full
0=Empty
ROVF
Reception Error (Overflow)
1=New data received with full RXSPI buffer
TUNF
Transmission Error (Underflow)
1=Transmission occurred with
no new data in TXSPI buffer
TXS
RXSPI Data Buffer Status (Read-Only)
1=Full
0=Empty
25
9
SPISTAT (0x1002)
SPISTATB (0x2802)
SPIFE
Transaction is complete on the external interface
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