ADSP-21368 SHARC Processor Hardware Reference B-1
B INTERRUPTS
This chapter provides a complete listing of the registers that are used to
configure and control interrupts. Table B-2 shows all the processor inter-
rupts, listed according to their bit position in the IRPTL, LIRPTL, and
IMASK registers. Also shown are the addresses of the interrupt vectors. Each
vector is separated by four memory locations.
Interrupt Vector Tables
The addresses in the vector table represent offsets from a base address. For
an interrupt vector table in internal RAM, the base address is 0x9 0000
and for internal ROM, the base address is 0x8 0000 (see Table B-1).
These are 48-bit addresses.
The interrupt name column in Table B-2 lists a mnemonic name for each
interrupt as they are defined by the definitions file (def21369.h) that
comes with the software development tools.
Table B-1. Interrupt Vector Table Base Address
Address
1
1 These are 48-bit addresses.
Description
0x0009 0000 Internal RAM (block 0)
0x0008 0000 Internal ROM (block 0)
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