Analog Devices SHARC ADSP-21368 User Manual

Processor Pin Descriptions
14-6 ADSP-21368 SHARC Processor Hardware Reference
Choosing EP Data Mode
The
FLAG/IRQ (0, 1, 2, 3) and DATA31–0 pins are completely independent.
Any mode of programming in one group does not affect the other.
Case 1
If 32-bit external SDRAM/FLASH/SRAM is used, then all data pins
should be connected to the memory device so that no other functionality
can be programmed in the data pins. In this case, use MODE 0. If flags
are required, they can be moved to the DPI SRU2.
Case 2
If 16-bit external SDRAM/FLASH/SRAM is used, and if 16 flag inputs
are required, then use MODE 1. Since 16 flags are required, set
FLAG/PWM_SEL = 0000. The flag input mode should be specified in the
FLAGS register.
Case 3
If 16-bit external SDRAM/FLASH/SRAM is used, and if 8 flag outputs
and 8 PWM outputs are required, then use MODE 1. Since 8 flags and
PWM outputs are required, set FLAG/PWM_SEL = 1100. (In this mode,
DATA31–24 are PWM outputs and DATA23–16 are flag outputs.) The flag
output mode should be specified in FLAGS register.
Case 4
If 8-bit external SDRAM/FLASH/SRAM is used, and if 8 flag inputs, 8
flag outputs, and 8 PWM outputs are required, then use MODE 2. Since
16 flags are required, then all flags on
DATA31–16 are programmed. This
means that there are not enough pins left for the PWM outputs (
DATA15–
8
). Therefore, program the PWM outputs on DATA23–16 and program the
FLAGS on DATA31–24 and DATA15–8. Set FLAGS/PWM_SEL = 0011. The flag
I/O direction should be specified in the
FLAGS register.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP