Input Data Port Registers
A-74 ADSP-21368 SHARC Processor Hardware Reference
Parallel Data Acquisition Port Control Register
(IDP_PP_CTL)
Setting IDP_PP_CTL[31] enables either the 20 DAI pins or the DATA31–8
pins to be used as a parallel input channel. These parallel words may be
packed into 32-bit words for efficiency. The data then flows through the
FIFO and is transferred by a dedicated DMA channel into the core’s
memory, as with any IDP channel.
The IDP_PP_CTL register, shown in Figure A-30 and described in
Table A-24, provides 20 mask bits that allow the input from any of the 20
pins to be ignored. The mask is specified by setting the IDP_Pxx_PDAPMASK
bits (bits 19–0 of the IDP_PP_CTL register) for the 20 parallel input signals.
For each of the parallel inputs, a bit is set (= 1) to indicate the bit is
unmasked and therefore its data can be passed on to be read, or masked
(= 0), so its data is not read. After this masking process, data gets passed
along to the packing unit.
For more information on the operation of the parallel data acquisition
port, see “Parallel Data Acquisition Port (PDAP)” on page 7-8. For infor-
mation on the pin muxing that is used in conjunction with this module,
see “Pin Multiplexing” on page 14-2.
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