ADSP-21368 SHARC Processor Hardware Reference 3-65
External Port
While executing the load mode register command, the unused address
pins are set to zero. During the first
SDCLK cycle following load mode reg-
ister, the SDC issues only NOP commands.
Alternatively, programs can use the Force LMR command by setting bit
22 (=1) in the SDCTL register. This command performs precharge all (if not
precharged already) followed by a mode register write. Unlike the standard
load mode register command, the eight CBR commands are not per-
formed. The correct usage of this bit is:
1. Force precharge (set bit 21)
2. Wait
3. Force LMR (set bit 22)
4. Wait
5. Eight CBR refresh cycles (set bit 20 eight times)
The order of these commands (step 3 and step 5, depending on SDRAM)
can be changed depending on the SDRAM requirements (see your
SDRAM vendors data sheet).
L
When the Force LMR bit is set, the load mode register command is
performed immediately. This is in contrast to the normal load
mode register command which requires a dummy access to be exe-
cuted (ADSP-2137x processors only).
Single Bank Activation
The bank activation command is required for first access to any internal
bank in SDRAM. Any subsequent access to the same internal bank but
different row will be preceded by a precharge and activation command to
that bank.
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