ADSP-21368 SHARC Processor Hardware Reference 5-43
Serial Ports
Unlike previous SHARC processors where programs had to poll the
SPORT control registers, on the ADSP-21367/8/9 and ADSP-2137x pro-
cessors, an interrupt is triggered and programs simply read the
SPERRSTAT
register (Figure 5-9). This reduces the processor overhead needed to do
the register polling.
The frame sync error (which sets the error bit) is triggered when an early
frame sync occurs during data transmission or reception. However, the
current transmit/receive operation continues without interruption. Note
that a frame sync error is not detected in following cases.
• When there is no active data transmit/receive and the frame sync
pulse occurs due to noise in the input signal an error is not gener-
ated (and is considered as valid frame sync).
• If there is a underflow or overflow error, frame sync errors are not
detected.
Each SPORT can generate an interrupt if a DERRA, DERRB, or FSYNCERR
error occurs. The SPERRCTLx registers control and report the status of the
interrupts generated by each SPORT (see Figure 5-9).
Data Word Formats
The format of the data words transmitted over the SPORTs is configured
by the
DTYPE, LSBF, SLEN, and PACK bits of the SPCTLx control registers.
This is discussed in the following sections.
Word Length
Serial ports can process word lengths of 3 to 32 bits for serial and multi-
channel modes and 8 to 32 bits for I
2
S and left-justified modes. Word
length is configured using the 5-bit
SLEN field in the SPCTLx control regis-
ters. Refer to Table 5-1 on page 5-11 for further information.
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