ADSP-21368 SHARC Processor Hardware Reference 1-7
Introduction
Processor Core
The processor core of the ADSP-21367/8/9 and ADSP-2137x processors
contain two processing elements (each with three computation units and
data register file), a program sequencer, two data address generators, a
timer, and an instruction cache. All digital signal processing occurs in the
processor core. For complete information, see the ADSP-21367/8/9 and
ADSP-2137x SHARC processors.
Processor Peripherals
The term processor peripherals refers to the multiple on-chip functional
blocks used to communicate with off-chip devices. The peripherals
include the JTAG, UART, serial ports, SPI ports, DAI/DPI components
(PCG, timers, and IDP are a few), and any external devices that connect
to the processor.
I/O Processor
The ADSP-21367/8/9 and ADSP-2137x processors input/output proces-
sor (IOP) manages the off-chip data I/O to alleviate the core of this
burden. Up to thirty-four channels of DMA are available on the
ADSP-21367/8/9 and ADSP-2137x processors—sixteen via the serial
ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface,
2 for the external port, and 2 for memory-to-memory transfers. The I/O
processor can perform DMA transfers between the peripherals and inter-
nal memory at the full core clock speed. The architecture of the internal
memory allows the IOP and the core to access internal memory simulta-
neously with no reduction in throughput.
Serial Ports. The processors feature up to eight synchronous serial ports
that provide an inexpensive interface to a wide variety of digital and
mixed-signal peripheral devices. The serial ports can operate at up to half
of the processor core clock rate with maximum of 50M bits per second.
Each serial port features two data pins that function as a pair based on the
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