ADSP-21368 SHARC Processor Hardware Reference A-153
Register Reference
16-Bit Transmit FIFO Register (TXTWI16)
The TWI FIFO transmit 16-bit register (TXTWI16, shown in Figure A-70)
holds a 16-bit data value written into the FIFO buffer. To reduce inter-
rupt output rates and peripheral bus access times, a 16-bit transfer data
access can be performed. Two data bytes can be written, effectively filling
the transmit FIFO buffer with a single access. The data is written in lit-
tle-endian byte order as shown in Figure A-70, where byte 0 is the first
byte to be transferred and byte 1 is the second byte to be transferred.
Figure A-70. 16-Bit Transmit FIFO Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
XMTDATA16[7:0]
TXTWI16 (0x4484)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
XMTDATA16[23:16]
Byte0–Transmitted first
Byte1–Transmitted second
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