Register Descriptions
12-8 ADSP-21368 SHARC Processor Hardware Reference
After servicing the interrupt source associated with a bit, programs must
clear that interrupt source bit. All bits are sticky and W1C-type. For more
information, see “Interrupt Source Register (TWIIRPTL)” on
page A-147.
Interrupt Enable Register
The TWI interrupt enable register (TWIIMASK) allows interrupt sources to
assert the interrupt output. Each enable bit corresponds with one inter-
rupt source bit in the TWI interrupt source register (
TWIIRPTL). Reading
and writing the TWI interrupt enable register does not affect the contents
of the TWI interrupt source register. For all bits, 0 = interrupt generation
disabled and 1 = interrupt generation enabled. For more information, see
“Interrupt Enable Register (TWIIMASK)” on page A-150.
8-Bit Transmit FIFO Register
The TWI 8-bit transmit FIFO register (TXTWI8) holds an 8-bit data value
written into the FIFO buffer. Transmit data is entered into the corre-
sponding transmit buffer in a first-in, first-out order. Although peripheral
bus writes are 32 bits, a write access to the TXTWI8 register adds only one
transmit data byte to the FIFO buffer. With each access, the transmit sta-
tus (TWITXS) field in the TWIFIFOSTAT register is updated. If an access is
performed while the FIFO buffer is full, the core waits until there is at
least one byte space in the transmit FIFO buffer and then completes the
write access. The bits in this register are write-only. For more information,
see “8-Bit Transmit FIFO Register (TXTWI8)” on page A-152.
16-Bit Transmit FIFO Register
The TWI 16-bit FIFO transmit register (TXTWI16) holds a 16-bit data
value written into the FIFO buffer. Although peripheral bus writes are 32
bits, a write access to the TXTWI16 register adds only two transmit data
bytes to the FIFO buffer. To reduce interrupt output rates and peripheral
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