Interrupts
9-24 ADSP-21368 SHARC Processor Hardware Reference
Interrupts
The following error/status bits can be used to interrupt the processor core.
• The DIR_LOCK, DIR_VALID, DIR_NOSTREAM and DIR_NOAUDIO bits can
generate interrupts. Parity errors and bi-phase errors are ORed
together to form a PARITY_BIPHASE_ERROR interrupt. Whenever
there is a change in channel status information, a
CHANNEL_STAT_CHANGE interrupt occurs.
• The DIR_BIPHASEERROR and DIR_VALID interrupts are one PCLK
pulse wide.
• All interrupts are processed through the interrupt controller which
can generate an interrupt on the rising or falling edge of the signal.
DAI Programming Examples
The following examples show how the S/PDIF receiver and transmitter
are programmed using the digital audio interface/SRU1.
S/PDIF Transmitter Programming Guidelines
The following guidelines are intended to help in programming the
S/PDIF transmitter.
Control Register
The DITCTL register contains control parameters for the S/PDIF transmit-
ter. The control parameters include transmitter enable, mute information,
oversampling clock division ratio, SCDF mode select and enable, serial
data input format select and validity, and channel status buffer selects. By
default, all the bits in this register are zero.
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