Setting AMI Modes
3-28 ADSP-21368 SHARC Processor Hardware Reference
Read/Write Throughput
For a wait state of 2 (which is the smallest wait state), the throughput is
shown in Table 3-11.
External Access Addressing
The AMI supports 16M words of external memory in bank1, bank2, and
bank3 and 14M words of external memory in bank0. The maximum
amount of external data is 64M bytes when the external bus width (set
using the BW bits 2–1 in the AMICTLx registers) is 32 bits on bank1, bank2,
or bank3.
The ADSP-21367/8/9 and ADSP-2137x processors have the ability to use
logical addressing when an external memory smaller than 32 bits is used.
When logical addresses are used, multiple external addresses seen by the
memory correspond to a single internal address, depending on the width
of the memory being accessed, and the packing mode setting of the AMI
or SDRAM controller. The following are examples of logical addressing.
Table 3-11. Read/Write Throughput
Bus Width Operation Throughput in SDCLK Cycles
32-bit Write One 32-bit word per 3 SDCLK cycles
32-bit Read One 32-bit word per 3 SDCLK cycles
16-bit Write One 32-bit word per 6 SDCLK cycles
16-bit Read One 32-bit word per 6 SDCLK cycles
8-bit Write One 32-bit word per 12 SDCLK cycles
8-bit Read One 32-bit word per 12 SDCLK cycles
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