ADSP-21368 SHARC Processor Hardware Reference 3-29
External Port
• For an external bus width of 32 bits, or when packing is disabled
with other bus widths (
PKDIS = 1 and BW = 16 bits or PKDIS = 1 and
BW = 8 bits), then the external physical memory is the same as the
lower 24 bits of bits 23–0 in the address being supplied to the
external port by the core or DMA controller.
• For an external bus width of 16 bits with packing enabled
(PKDIS = 0), the external physical address ADDR23–0 generation is
ADDR23–1 = bits 22–0 in the address being supplied to the external
port by the core or DMA controller. Here, ADDR[0] corresponds to
the 1st/2nd 16-bit word.
• For an external bus width of 8 bits with packing enabled
(PKDIS = 0), the external physical address ADDR23–0 generation is
ADDR23–2 = bits 21–0 in the address being supplied to the external
port by the core or DMA controller. Here, ADDR1–0 corresponds to
the 1st/2nd/3rd/4th 8-bit word.
The external physical address map is shown in Table 3-12.
Table 3-12. AMI Address Memory Map
Bus Width External
Memory BANK
External Physical Address
(on ADDR23–0)
32-bit (or PKDIS=1) 0 0x20_0000 to 0xFF_FFFF
32-bit (or PKDIS=1) 1, 2, and 3 0x00_0000 to 0xFF_FFFF
16-bit (and PKDIS=0) 0 0x40_0000 to 0xFF_FFFF
16-bit (and PKDIS=0) 1, 2, and 3 0x00_0000 to 0xFF_FFFF
8-bit (and PKDIS=0) 0 0x80_0000 to 0xFF_FFFF
8-bit (and PKDIS=0) 1, 2, and 3 0x00_0000 to 0xFF_FFFF
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