Analog Devices SHARC ADSP-21368 - SPI DMA Registers; SPI DMA Configuration Registers; Spidmacb; SPI DMA Start Address Registers (IISPI, IISPIB

ADSP-21368 SHARC Processor Hardware Reference A-61
Register Reference
SPI DMA Registers
There are ten SPI DMA-specific registers:
• “SPI DMA Configuration Registers (SPIDMAC, SPIDMACB)”
on page A-62
• “SPI DMA Start Address Registers (IISPI, IISPIB)” on page A-64
• “SPI DMA Address Modify Registers (IMSPI, IMSPIB)” on
page A-64
• “SPI DMA Word Count Registers (CSPI, CSPIB)” on page A-64
• “SPI DMA Chain Pointer Registers (CPSPI, CPSPIB)” on
page A-65
For information on configuring DMA using the SPI, see “Setting Up and
Starting Chained DMA over the SPI” on page 2-42.
324 13.9 MHz
432 10.4 MHz
32,767, (0x7FFF) 262136 1.3 KHz
Table A-14. SPI Master Baud Rate Example (Cont’d)
BAUDR
(Decimal Value)
SPI CLock Divide Factor Baud Rate for CCLK