Serial Port Registers
A-50 ADSP-21368 SHARC Processor Hardware Reference
SPORT DMA Index Registers (IISPx)
The IISPx register is 19 bits wide. It holds an address and acts as a pointer
to memory for a DMA transfer. For more information, see “I/O Proces-
sor” on page 2-1. The addresses of the IISPx registers are:
The reset value for these registers is undefined.
SPORT DMA Modifier Registers (IMSPx)
The IMSPx register is 16 bits wide and it provides the increment or step
size by which an IISPx register is post-modified during a DMA operation.
For more information, see “I/O Processor” on page 2-1. The reset value
for these registers is undefined. The addresses of the IMSPx registers are:
IISP0A – 0xC40 IISP0B – 0xC44
IISP1A – 0xC48 IISP1B – 0xC4C
IISP2A – 0x440 IISP2B – 0x444
IISP3A – 0x448 IISP3B – 0x44C
IISP4A – 0x840 IISP4B – 0x844
IISP5A – 0x848 IISP5B – 0x84C
IISP6A – 0x4840 IISP6B – 0x4844
IISP7A – 0x4848 IISP7B – 0x484C
IMSP0A – 0xC41 IMSP0B – 0xC45
IMSP1A – 0xC49 IMSP1B – 0xC4D
IMSP2A – 0x441 IMSP2B – 0x445
IMSP3A – 0x449 IMSP3B – 0x44D
IMSP4A – 0x841 IMSP4B – 0x845
IMSP5A – 0x849 IMSP5B – 0x84D
IMSP6A – 0x4841 IMSP6B – 0x4845
IMSP7A – 0x4849 IMSP7B – 0x484D
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