ADSP-21368 SHARC Processor Hardware Reference A-65
Register Reference
SPI DMA Chain Pointer Registers (CPSPI, CPSPIB)
The reset values for these registers are undefined. These 20-bit, read-write
SPI registers contain the address of the next TCB when DMA chaining is
enabled. Their addresses are 0x1083 (for
CPSPI) and 0x2883 (for CPSPIB).
Input Data Port Registers
The input data port (IDP) provides an additional input path to the pro-
cessor core. The IDP is configurable as eight channels of serial data or
seven channels of serial data and a single channel of up to a 20-bit wide
parallel data. Six registers are used to specify modes, track status of inputs
and outputs, and permit the IDP FIFO buffer to be read.
• “Input Data Port Control Register 0 (IDP_CTL0)” on page A-66
• “Input Data Port Control Register 1 (IDP_CTL1)” on page A-68
• “Input Data Port FIFO Register (IDP_FIFO)” on page A-69
• “Input Data Port DMA Control Registers” on page A-70
• “Input Data Port Ping-Pong DMA Registers” on page A-72
• “Parallel Data Acquisition Port Control Register (IDP_PP_CTL)”
on page A-74
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