ADSP-21368 SHARC Processor Hardware Reference 14-55
System Design
When a new external memory instruction fetch occurs on the
ADSP-2137x processor due to a jump from internal to external memory,
or after a cache hit while executing instructions from external memory,
there is one stall cycle present in the fetch1 stage. This stall avoids
resource conflicts at the cache interface.
The
FLUSH CACHE instruction has an effect latency of one instruction when
executing program instructions from internal memory, and two instruc-
tions when executing from external memory. This applies to the
ADSP-2137x processors only.
A one cycle stall is generated whenever an instruction that contains a con-
ditional external memory access is in the decode stage, where the
evaluation of the condition is dependent on the outcome of the previous
instruction in address stage. It applies to all kinds of conditions, except for
conditions based on FLAG status. The following is an example.
f12=f11+f10;
if eq then dm(ext) = r0;
There is one cycle latency between a multiplier status change and an arith-
metic loop abort. This extra cycle is machine cycle and not the instruction
cycle. Therefore, if there is a pipeline stall (due to external memory access
etc.) then the latency does not apply.
IOP Register Stalls
Read of the IOP registers takes a minimum of four cycles, therefore the
processor stalls for at least three cycles.
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