SRC Operation
10-20 ADSP-21368 SHARC Processor Hardware Reference
Muting can also be controlled in software using the
MUTE bits
(SRCx_SOFTMUTE, SRCx_HARD_MUTE, SRCx_AUTO_MUTE) in the SRC control
register (SRCCTL) as described below. For more information, see “SRC
Registers” on page 10-21.
Soft Mute
When the SRCx_SOFTMUTE bit in the SRCCTL register is set, the MUTE_IN sig-
nal is asserted, and the SRC performs a soft mute by linearly decreasing
the input data to the SRC FIFO to zero, (–144 dB attenuation) as
described for automatic hardware muting.
Hard Mute
When the SRCx_HARD_MUTE bit in the SRCCTL register is set, the SRC imme-
diately mutes the input data to the SRC FIFO to zero, (–144 dB
attenuation).
Auto Mute
When the SRCx_AUTO_MUTE bit in the SRCCTL register is set, the SRC com-
municates with the SPDIF receiver peripheral to determine when the
input should mute. Each SRC is connected to the NOAUDIO bits in the out-
put of the SPDIF receiver (see “Receiver Status Register (DIRSTAT)” on
page A-94). When this signal is asserted, the SRC immediately mutes the
input data to the SRC FIFO to zero, (–144 dB attenuation). This mode is
useful for automatic detection of non-PCM audio data received from the
S/PDIF receiver.
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