ADSP-21368 SHARC Processor Hardware Reference 13-9
Precision Clock Generators
The frequency of the frame sync output is determined by:
When the divisor is set to any value other than 0 or 1, the processors oper-
ate in normal mode.
The frame sync divisors (
FSxDIV bits) are specified in bits 19–0 of the cor-
responding PCG control registers (PCG_CTLx0). The pulse width of the
frame sync output is equal to the number of input clock periods specified
in the 16-bit field of the corresponding PCG pulse width register (PCG_PW
for A and B, PCG_PW2 for C and D). Bits 15–0 specify the pulse width of
frame sync A and C, and bits 31–16 specify the pulse width of frame sync
B and D.
Phase Shift
Phase shift is a frame sync parameter that defines the phase shift of the
frame sync with respect to the clock of the same unit. This feature allows
shifting of the frame sync signal in time relative to clock signals. Frame
sync phase shifting is often required by peripherals that need a frame sync
signal to lead or lag a clock signal.
The amount of phase shifting is specified as a 20-bit value in the
FSAPHASE_HI bit field (bits 29–20) of the appropriate PCG_CTLAO register
and in the
FSAPHASE_LO bit field (bits 29–20) of the PCG_CTLA1 register for
unit A. A single 20-bit value spans these two bit fields. The upper half of
the word (bits 19–10) resides in the PCG_CTLAO register, and the lower half
(bits 9–0) resides in the PCG_CTLA1 register.
Similarly, the phase shift for frame syncs B, C, and D is specified in the
corresponding PCG_CTLxO and PCG_CTLx1 registers.
Frequency of Clock Input
Frame Sync Divisor
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