Analog Devices SHARC ADSP-21368 User Manual

Clock Derivation
14-14 ADSP-21368 SHARC Processor Hardware Reference
Power Management Control Register
The ADSP-21367/8/9 and ADSP-2137x processors have a power manage-
ment control register (PMCTL) that allows programs to determine the
amount of power dissipated. This includes the ability to program the PLL
dynamically in software, achieving a slower core instruction rate that min-
imizes power use. For a complete register description, see “Power
Management Control Register (PMCTL)” on page A-170.
The PMCTL register also allows programs to disable the clock source to a
particular processor peripheral, for example the serial ports or the timers,
to further conserve power. By default, each peripheral block has its inter-
nal clock enabled only after it is initialized. Programs can use the PMCTL
register to turn the specific peripheral off after the application no longer
needs it. After reset, these peripheral clocks are not enabled until the
peripheral itself is initialized by the program. Listing 14-1 and
Listing 14-2 show some clock management options.
Listing 14-1. Using the System Clock for the SPI Module
ustat2 = dm(PMCTL);
bit set ustat2 SPIPDN; /* disable internal peripheral clock for
SPI module. SPIPDN is defined as bit
30 of PMCTL */
dm(PMCTL) = ustat2;

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP