ADSP-21368 SHARC Processor Hardware Reference 3-51
External Port
This means
RDIV is 0x406 (hex) and the SDRAM refresh rate control reg-
ister is written with 0x406.
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The RDIV value must be programmed to a nonzero value if the
SDRAM controller is enabled. When RDIV = 0, operation of the
SDRAM controller is not supported and can produce undesirable
behavior. Values for RDIV can range from 0x001 to 0xFFF.
For details on the SDROPT and SDMODIFY bits see, “SDRAM Read Optimi-
zation” on page 3-75.
SDRAM Initialization
Before executing the SDC power-up sequence, ensure that:
1. The SDRAM receives stable power and is clocked for the proper
amount of time, as specified by the SDRAM specification.
2. The SDPSS bit is set to 1 to enable the SDRAM power-up sequence.
3. A read or write access occurs to enabled SDRAM address space in
order to have the external bus granted to the SDC. This allows the
SDRAM power-up sequence to occur.
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There is a long latency for this first access to SDRAM because the
power-up sequence takes many cycles to complete.
SDRAM Address Mapping
The address that is seen from the processor core and DMA controller is
referred to as internal address space IA[31–0] in the following sections.
The internal address is divided into three parts to generate the SDRAM
row, column, and bank addresses as shown in Figure 3-8.
RDIV
133 10
6
()64×× 10
3–
()×
8192
-----------------------------------------------------------------
⎝⎠
⎜⎟
⎛⎞
63+() 1030=–=
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