ADSP-21368 SHARC Processor Hardware Reference 5-21
Serial Ports
The I
2
S bus transmits audio data and control signals over separate lines.
The data line carries two multiplexed data channels—the left channel and
the right channel. In I
2
S mode, if both channels on a SPORT are set up to
transmit, then SPORT transmit channels (TXSPxA and TXSPxB) transmit
simultaneously, each transmitting left and right I
2
S channels. If both
channels on a SPORT are set up to receive, the SPORT receive channels
(RXSPxA and RXSPxB) receive simultaneously, each receiving left and right
I
2
S channels. Data is transmitted in MSB-first format.
L
Companding is not supported in I
2
S mode.
Each SPORT transmit or receive channel has a channel enable, a DMA
enable, and chaining enable bits in its SPCTLx control register. The
SPORTx_FS signal is used as the transmit and/or receive word select signal.
DMA-driven or interrupt-driven data transfers can also be selected using
bits in the SPCTLx register.
Setting the Internal Serial Clock and Frame Sync Rates
The serial clock rate for internal clocks can be set using the CLKDIV bit
field in the DIVx register and the frame sync rate for internal frame sync
can be set using the FSDIV bit field in the DIVx register. For details, see
Figure 5-10 on page 5-70.
I
2
S Mode Control Bits
Table 5-1 on page 5-5 shows that I
2
S mode is simply a subset of the
left-justified sample pair mode which can be invoked by setting
OPMODE = 1, LAFS = 0, and FRFS = 1.
L
If FRFS = 0, the Tx/Rx is on the right channel first. For normal I
2
S
operation (FRFS = 1), the Tx/Rx starts on the left channel first.
To Next Page
Loading...
Need help?
General
