ADSP-21368 SHARC Processor Hardware Reference 5-39
Serial Ports
Active Low Versus Active High Frame Syncs
Frame sync signals may be active high or active low (for example,
inverted). The LFS bit (bit 16) of the SPCTLx control registers determines
the frame sync’s logic level:
• When
LFS is cleared (=0), the corresponding frame sync signal is
active high.
• When
LFS is set (=1), the corresponding frame sync signal is active
low.
Active high frame syncs are the default. The LFS bit is initialized to zero
after a processor reset.
Sampling Edge for Data and Frame Syncs
Data and frame syncs can be sampled on the rising or falling edges of the
SPORT clock signals. The CKRE bit of the SPCTLx control registers selects
the sampling edge.
For sampling receive data and frame syncs, setting CKRE to 1 in the SPCTLx
registers selects the rising edge of SPORTx_CLK. When CKRE is cleared (=0),
the processor selects the falling edge of SPORTx_CLK for sampling receive
data and frame syncs. Note that transmit data and frame sync signals
change their state on the clock edge that is not selected.
For example, the transmit and receive functions of any two SPORTs con-
nected together should always select the same value for
CKRE so
internally-generated signals are driven on one edge and received signals are
sampled on the opposite edge.
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