Frame Sync Options
5-40 ADSP-21368 SHARC Processor Hardware Reference
Early Versus Late Frame Syncs
Frame sync signals can be early or late. Frame sync signals can occur dur-
ing the first bit of each data word or during the serial clock cycle
immediately preceding the first bit. The LAFS bit of the SPCTLx control
registers configures this option.
When LAFS is cleared (=0), early frame syncs are configured. This is the
normal mode of operation. In this mode, the first bit of the transmit data
word is available (and the first bit of the receive data word is latched) in
the serial clock cycle after the frame sync is asserted. The frame sync is not
checked again until the entire word has been transmitted (or received). In
multichannel operation, this is the case when the frame delay is one clock
cycle.
If data transmission is continuous in early framing mode (for example, the
last bit of each word is immediately followed by the first bit of the next
word), the frame sync signal occurs during the last bit of each word. Inter-
nally-generated frame syncs are asserted for one clock cycle in early
framing mode.
When LAFS is set (=1), late frame syncs are configured. In this mode, the
first bit of the transmit data word is available (and the first bit of the
receive data word is latched) in the same serial clock cycle that the frame
sync is asserted. In multichannel operation, this is the case when frame
delay is zero. Receive data bits are latched by serial clock edges, but the
frame sync signal is checked only during the first bit of each word. Inter-
nally-generated frame syncs remain asserted for the entire length of the
data word in late framing mode. Externally-generated frame syncs are only
checked during the first bit. They do not need to be asserted after that
time period.
Figure 5-8 illustrates the two modes of frame signal timing.
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