ADSP-21368 SHARC Processor Hardware Reference 4-13
Digital Audio/Digital Peripheral Interfaces
Although not strictly necessary, it is recommended programming practice
to tie the pin buffer input to logic low whenever the pin buffer enable is
tied to logic low. By default, the pin buffer enables are connected to
SPORT pin enable signals that may change value. Tying the pin buffer
input low decouples the line from irrelevant signals and can make code
easier to debug. It also ensures that no voltage is driven by the pin if a bug
in your code accidentally asserts the pin enable.
Bidirectional Pin Buffers
All peripherals within the DAI and DPI that have bidirectional pins gen-
erate a corresponding pin enable signal. Typically, the settings within a
peripheral’s control registers determine if a bidirectional pin is an input or
an output, and is then driven accordingly. Both the peripheral control reg-
isters and the configuration of the SRUs can effect the direction of signal
flow in a pin buffer.
Figure 4-8. Pin Buffer as Input
IN
OUT
PIN
ENABLE
DAI_PBxx_I
DAI_PBxx_O
PBENxx_I
EXTERNAL
PACKAGE
CONNECTION
PIN
INTERFACE
TO SRU
PAD
DRIVER
PIN BUFFER
OUTPUT
PIN BUFFER
INPUT
(NOT USED)
PIN BUFFER
ENABLE
(= LOW)
DAI_PBxx_O
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