ADSP-21368 SHARC Processor Hardware Reference 5-71
Serial Ports
Use the following equation to determine the value of
FSDIV, given the
serial clock frequency and desired frame sync frequency:
The frame sync is continuously active when FSDIV = 0. The value of FSDIV
should not be less than the serial word length minus one (the value of the
SLEN field in the SPORT control registers), as this may cause an external
device to abort the current operation or cause other unpredictable results.
If the SPORT is not being used, the FSDIV divisor can be used as a counter
for dividing an external clock or for generating a periodic pulse or periodic
interrupt. The SPORT must be enabled for this mode of operation to
work properly.
Exercise caution when operating with externally-generated transmit clocks
near the frequency of one-eighth of the processor’s internal clock. There is
a delay between when the clock arrives at the SPORTx_CLK node and when
data is output. This delay may limit the receiver’s speed of operation.
Refer to the product-specific data sheet for exact timing specifications.
Externally-generated late transmit frame syncs also experience a delay
from when they arrive to when data is output. This can also limit the max-
imum serial clock speed. Refer to the product-specific data sheet for exact
timing specifications.
SPORT Reset
There are two ways to reset the SPORTs, via software or hardware. Each
method has a different effect on the SPORT.
FSDIV
f
SPORTx_CLK
f
SPORTx_FS
----------------------------
1–=
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