Peripheral Interrupt Priority Control Registers
A-168 ADSP-21368 SHARC Processor Hardware Reference
Peripheral Interrupt Priority1 Control
Register (PICR1)
This register controls programmable peripheral interrupts 6–11 and the
default sources shown in Figure A-80. This 32-bit, read/write register is
located at address 0x2201. The reset value of this register is 0x16A4A0E6.
Figure A-80. PICR1 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
P11I
SPORT2 Interrupt
Programmable Interrupt 7
P7I
P9I
External Port DMA
Channel 0 Interrupt
Programmable Interrupt 9
SPORT0 Interrupt
Programmable Interrupt 6
P6I
SPORT4 Interrupt
Programmable Interrupt 8
P8I
P10I
General-Purpose I/O Timer1 Interrupt
Programmable Interrupt 10
PICR1 (0x2201)
SPORT7 Interrupt
Programmable Interrupt 11
RESET=0x16A4A0E6
To Next Page
Loading...
