Analog Devices SHARC ADSP-21368 - Polling;Status-Driven I;O

Configuring IOP/Core Interaction
2-12 ADSP-21368 SHARC Processor Hardware Reference
2. Add sufficient
NOP instructions after a write. In the worst case pro-
grams need to add ten NOP instructions after a write as shown in the
example code below.
isr_code:
R0 = 0x0;
dm(SPICTL) = R0; /* disable SPI */
nop; nop; nop; nop; nop;
nop; nop; nop; nop; nop;
rti;
3. Read a status register from the same peripheral block to check
whether the interrupt has cleared.
Polling/Status-Driven I/O
The second method of controlling I/O is through status polling. The I/O
processor monitors the status of data transfers on DMA channels and indi-
cates interrupt status in the IRPTL, LIRPTL, DAI_IRPTL_H, and DAI_IRPTL_L
registers. Note that because polling uses processor resources it is not as
efficient as an interrupt-driven system. Also note that polling the DMA
status registers reduces I/O bandwidth. The following provide more infor-
mation on the registers that control and monitor I/O processes.
• All the bits in the
IRPTL and LIRPTL registers are shown in “Inter-
rupt Latch Register (IRPTL)” on page B-13 and “Interrupt
Register (LIRPTL)” on page B-6.
• Figure A-44 on page A-114 lists all the bits in the
DAI_IRPTL_H and
DAI_IRPTL_L registers.
The DMA controller in the ADSP-21367/8/9 and ADSP-2137x proces-
sors maintains the status information of the channels in each of the
peripherals registers, SPMCTLx, EPDMACTL, DAI_STAT, DPI_PIN_STAT,
RXSTAT_UACx, TXSTAT_UACx and SPIDMAC. More information on these regis-
ters can be found at the following locations.