ADSP-21368 SHARC Processor Hardware Reference 6-37
Serial Peripheral Interface Ports
Transmission Error Bit (TUNF)
The TUNF bit is set in the SPISTAT register when all of the conditions of
transmission are met and there is no new data in the TXSPI buffer (TXSPI is
empty). In this case, the transmission contents depend on the state of the
SENDZ bit in the SPICTL register. The TUNF bit is cleared by a W1C-type
software operation.
Reception Error Bit (ROVF)
The ROVF flag is set in the SPISTAT register when a new transfer has com-
pleted before the previous data could be read from the RXSPI register. This
bit indicates that a new word was received while the receive buffer was
full. The ROVF flag is cleared by a W1C-type software operation. The state
of the GM bit in the SPICTL register determines whether the RXSPI register is
updated with the newly received data or whether that new data is
discarded.
Transmit Collision Error Bit (TXCOL)
The TXCOL flag is set in the SPISTAT register when a write to the TXSPI reg-
ister coincides with the load of the shift register. The write to TXSPI can be
initiated by the core or by DMA. This bit indicates that corrupt data may
have been loaded into the shift register and transmitted. In this case, the
data in TXSPI may not match what was transmitted. This error can easily
be avoided by proper software control. The
TXCOL bit is cleared by a
W1C-type software operation.
L
This bit is never set when the SPI is configured as a slave with
CPHASE = 0. The collision may occur, but it cannot be detected.
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