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ADSP-21368 SHARC Processor Hardware Reference 5-47

Serial Ports

Linear transfers occur in the primary channel, if the channel is active and

companding is not selected for that channel. Companded transfers occur

if the channel is active and companding is selected for that channel. The

multichannel compand select registers,

SPxCCSy, specify the transmit and

receive channels that are companded when multichannel mode is enabled.

For more information, see “SPORT Compand Registers (SPxCCSy)” on

page A-47.

Transmit or receive sign extension is selected by bit 0 of DTYPE in the

SPCTLx registers and is common to all transmit or receive channels. If bit 0

of DTYPE is set, sign extension occurs on selected channels that do not have

companding selected. If this bit is not set, the word contains zeros in the

MSB positions. Companding is not supported for B channel. For B chan-

nels, transmit or receive sign extension is selected by bit 0 of DTYPE in the

SPCTLx registers.

Companding

Companding (compressing/expanding) is the process of logarithmically

encoding and decoding data to minimize the number of bits that must be

sent. The processor’s SPORTs support the two most widely used com-

panding algorithms, A-law and μ-law, performed according to the CCITT

G.711 specification. The type of companding can be selected indepen-

dently for each SPORT. Companding is selected by the DTYPE field of the

SPCTLx registers.

Companding is supported on the A channel only. SPORT0, 2, 4

and 6 primary channels are capable of compression, while SPORTs

1, 3, 5 and 7 primary channels are capable of expansion.

In multichannel mode, when companding and expansion is

enabled, the number of channels must be programmed via the NCH

bit in the

SPMCTLx registers before writing to the transmit FIFO.

The

SPxCSn and SPxCCsn registers should also be written before

writing to transmit FIFO.

Analog Devices SHARC ADSP-21368 User Manual

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