ADSP-21368 SHARC Processor Hardware Reference 9-25
S/PDIF Transmitter/Receiver
SRU1 Programming for Input and Output Streams
Signal routing unit 1 (SRU1) is used to connect the S/PDIF transmitter
bi-phase data out to the output pins or to the S/PDIF receiver. The serial
data input and the over sampling clock input also needs to be routed
through SRU1. See For more information, see “Group A Connections—
Clock Signals” on page 4-19 and “Group B Connections—Data Signals”
on page 4-25.
Control Register Programming and Enable
After SRU1 programming is complete, if the channel status or validity
buffer needs enabling, write to the buffers first with the required data and
then enable the buffers using the
DIT_CHANBUF bit in the DITCTL register.
Also write other control values such as DIT_SMODEIN, and DIT_FREQ and
enable the transmitter by setting the DIT_EN bit.
S/PDIF Receiver Programming Guidelines
The following guidelines are intended to help in programming the
S/PDIF receiver.
Control Register
The S/PDIF receiver is enabled at default to receive in two channel mode.
Therefore, if the receiver is not used, programs should disable the digital
PLL to avoid unnecessary switching. This is accomplished by writing into
the
DIR_PLLDIS bit (bit 7) in the DIRCTL register. In most cases, when the
S/PDIF receiver is used, this register does not need to be changed. For a
detailed description of this register, see “Receiver Control Register
(DIRCTL)” on page A-92.
The
DIRCTL register contains control parameters for the S/PDIF receiver.
The control parameters include mute information, error controls, SCDF
mode select and enable, and digital PLL disable.
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