General-Purpose I/O (GPIO) and Flags
4-64 ADSP-21368 SHARC Processor Hardware Reference
The pin enable control registers activate the drive buffer for each of the 14
DPI pins. When the pins are not enabled (driven), they can be used as
inputs.
General-Purpose I/O (GPIO) and Flags
Each interface is capable of using its pins for general-purpose I/O and
flags. The sections that follow describe this use for each interface.
DAI GPIO and Flags
In the DAI, any of the pins may also be considered general-purpose
input/output (GPIO) pins. Each of the DAI pins can also be set to drive a
high or low logic level signal to assert signals. They can also be connected
to miscellaneous signals and used as interrupt sources or as control inputs
to other blocks.
100101 37 TWI_SCLK_OE Serial clock output enable from TWI
100110 38 EXT_MISC_3 Miscellaneous control 3
100111 39 EXT_MISC_4 Miscellaneous control 4
101000 40 EXT_MISC_5 Miscellaneous control 5
101001 41 EXT_MISC_6 Miscellaneous control 6
101010 42 EXT_MISC_7 Miscellaneous control 7
101011 43 EXT_MISC_8 Miscellaneous control 8
101100–
111111
44-63 Reserved
Table 4-13. Group C Signals (Cont’d)
Binary Decimal Signal Description
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