ADSP-21368 SHARC Processor Hardware Reference 14-37
System Design
• Ground Planes and Layer Stacking
• Terminations
•Vias
• Power Systems
• Connectors
• Ribbon Cables
• Clock Distribution
• Clock Oscillators
High-Speed Digital Design: A Handbook of Black Magic, Johnson & Gra-
ham, Prentice Hall, Inc., ISBN 0-13-395724-1.
Booting
When a processor is initially powered up, its internal SRAM is undefined.
Before actual program execution can begin, the application must be
loaded from an external non-volatile source such as flash memory or a host
processor. This process is known as bootstrap loading or booting and is
automatically performed by the processor after power-up or after a soft-
ware reset.
The ADSP-21367/8/9 and ADSP-2137x processors support three booting
modes—EPROM, SPI master and SPI slave. Each of these modes uses the
following general procedure:
1. At reset, the processor is hardwired to load 256 48-bit instruction
words through a DMA starting at location 0x90000. In this sec-
tion, these instructions are referred to as the boot kernel or loader
kernel.
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