ADSP-21368 SHARC Processor Hardware Reference 9-19
S/PDIF Transmitter/Receiver
• DIR_TDMCLK_O is the receiver TDM clock output. This signal
can be routed to any of the external pins or to one of the serial
receivers (SPORT, input data port) through SRU1.
• DIR_LRCLK_FB is the external PLL feedback point connection.
• DIR_LRCLK_REF is the external PLL reference point connection.
Phase-Locked Loop
The phase-locked loop for the AES3/SPDIF receiver is intended to recover
the clock that generated the AES3/SPDIF bi-phase encoded stream. This
clock is used by the receiver to clock in the bi-phase encoded data stream
and also to provide clocks for either the serial ports, sample rate converter,
or AES3/SPDIF transmitter. The recovered clock may also be used exter-
nally to the chip for clocking D/A and A/D converters.
In order to maintain performance, jitter on the clock is sourced to several
peripherals. Jitter on the recovered clock must be less than 200 ps and, if
possible, less than 100 ps across all the sampling frequencies ranging from
27.2 kHz to 220.8 kHz (32 kHz – 15% and 192 kHz + 15%). Further-
more, once the PLL achieves lock, it is able to vary ±15% in frequency
over time. This allows for applications that do not use PLL unlocking.
The receiver can be used with the on-chip digital PLL or with an external
analog PLL. There are various performance characteristics to consider
when configuring for analog PLL mode, and more information can be
found on the Analog Devices Web site.
Channel Status Decoding
The S/PDIF receiver processes compressed as well as non-linear audio data
according to the supported standards. The following sections describe how
the S/PDIF receiver handles different data.
To Next Page
Loading...
Need help?
General
