Power Management Control Register (PMCTL)
A-170 ADSP-21368 SHARC Processor Hardware Reference
Peripheral Interrupt Priority3 Control
Register (PICR3)
This register controls programmable peripheral interrupt 18 as shown in
Figure A-82. This 32-bit, read/write register is located at address 0x2203.
The reset value of this register is 0x00000012.
Power Management Control
Register (PMCTL)
The power management control register is a 32-bit, memory-mapped reg-
ister. The
PMCTL register’s addresses is 0x2000. This register contains bits
to control phase-lock loop (PLL) multiplier and divider (both input and
output) values, PLL bypass mode, and clock enabling control for peripher-
als (see Figure A-83 and Table A-70). This register also contains status
bits, which keep track of the status of the CLK_CFG pins (read-only).
The core can write to all bits except the read-only status bits. The
DIVEN
bit is a logical bit, that is, it can be set, but on reads it always responds
with zero.
Figure A-82. PICR3 Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0000000000000000
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000000000000000
Reserved
P18I
SPI B Interrupt
Programmable Interrupt 18
PICR3 (0x2203)
Reserved
RESET=0x00000012
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