ADSP-21368 SHARC Processor Hardware Reference 8-7
Pulse Width Modulation
maximum value they can contain is 0x3FF (= 1023) which corresponds to
a maximum programmed dead time of:
This equates to an f
PCLK
rate of 100 MHz. Note that the dead time can be
programmed to be 0 by writing 0 to the PWMDTx registers (see “PWM Dead
Time Registers (PWMDTx)” on page A-85.
Duty Cycles
The two 16-bit read/write duty cycle registers, PWMA and PWMB control the
duty cycles of the four PWM output signals on the PWM pins when not
in switch reluctance mode. The two’s-complement integer value in the
PWMA register controls the duty cycle of the signals on pwm_ah and pwm_al.
The two’s-complement integer value in the PWMB register controls the duty
cycle of the signals on pwm_bh and pwm_bl. The duty cycle registers are pro-
grammed in two’s-complement integer counts of the fundamental time
unit, t
PCLK
, and define the desired on-time of the high-side PWM signal
produced by the three-phase timing unit over half the PWM period. The
duty cycle register range is from:
(–PWPERIOD ÷ 2 – PWMDT) to (+PWPERIOD ÷ 2 + PWMDT)
which, by definition, is scaled such that a value of 0 represents a 50%
PWM duty cycle. The switching signals produced by the three-phase tim-
ing unit are also adjusted to incorporate the programmed dead time value
in the
PWMDT register. The three-phase timing unit produces active low sig-
nals so that a low level corresponds to a command to turn on the
associated power device.
T
dmax,
1023 2× t
PCLK
× 1023 2× 10 10
9–
×× 20.5μs==d=
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