DAI/DPI Interrupt Controller
4-66 ADSP-21368 SHARC Processor Hardware Reference
generate an interrupt, a signal that a serial port has received data that must
be processed, a signal that an SPI has either transmitted or received data,
and other software interrupts like the insertion of a trap that causes a
breakpoint—all are conditions, which identify to the core that an event
has occurred.
Since DAI specific events generally occur infrequently, the DAI IC classi-
fies such interrupts as either high or low priority interrupts. Within these
broad categories, programs can indicate which interrupts are high and
which are classified as low.
Any interrupt causes a four-cycle stall, since it forces the core to stop
instruction execution while in process, then vector to the interrupt service
routine (ISR), (which is basically an interrupt vector table (IVT) lookup),
then proceed to implement the instruction referenced in the IVT. For
more information, see Appendix B, Interrupts.
When an interrupt from the DAI needs servicing, one of the two core
interrupt service routines (ISR) must query the DAI’s interrupt controller
to determine the source(s). Sources can be any one or more of the inter-
rupt controller’s 32 configurable channels (
DAI_INT[31:0]). For more
information, see “DAI Interrupt Controller Registers” on page A-112.
DAI events trigger two interrupts in the primary IVT—one each for low
or high priority.
DAI Interrupts
There are several registers in the DAI interrupt controller that can be con-
figured to control how the DAI interrupts are reported to and serviced by
the core’s interrupt controller. Among other options, each DAI interrupt
can be mapped either as a high or low priority interrupt in the primary
interrupt controller. Certain DAI interrupts can be triggered on either the
rising or the falling edge of the signals, and each DAI interrupt can also be
independently masked.
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