ADSP-21368 SHARC Processor Hardware Reference 6-11
Serial Peripheral Interface Ports
In master mode, if the transmit buffer remains empty, or the receive
buffer remains full, the device operates according to the states of the
SENDZ
and GM bits in the SPICTLx registers.
•If SENDZ = 1 and the transmit buffer is empty, the device repeatedly
transmits zeros on the MOSI pin. One word is transmitted for each
new transfer initiate command.
•If SENDZ = 0 and the transmit buffer is empty, the device repeatedly
transmits the last word it transmitted before the transmit buffer
became empty.
•If GM = 1 and the receive buffer is full, the device continues to
receive new data from the MISO pin, overwriting the older data in
the RXSPI buffer.
•If GM = 0 and the receive buffer is full, the incoming data is dis-
carded, and the RXSPI register is not updated.
Slave Mode Operation
When a device is enabled as a slave (and DMA mode is not selected), the
start of a transfer is triggered by a transition of the SPIDS select signal to
the active state (LOW) or by the first active edge of the clock (SPICLK),
depending on the state of CPHASE.
The following steps illustrate SPI operation in slave mode:
1. Write to the
SPICTLx registers making sure that the slave’s configu-
ration matches the current SPI master.
2. To prepare for the data transfer, write the data to be transmitted
into the TXSPIx registers.
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