Shared Memory Interface
3-82 ADSP-21368 SHARC Processor Hardware Reference
Conditional instructions can be written that depend upon whether the
processor is the current bus master in a shared memory system. The
assembly language mnemonic for this condition code is
BM, and its com-
plement is Not BM (not bus master). The BM condition indicates whether
the processor is the current bus master. For more information, see the
“Conditional Sequencing” section in the ADSP-2136x SHARC Processor
Programming Reference, “Program Sequencer” chapter. To use the bus
master condition, the condition code select (CSEL) field in the MODE1 regis-
ter must be zero or the condition is always evaluated as false.
Bus Arbitration Protocol
The bus request (BR1-4) pins are connected between each processor in a
shared memory system, where the number of BRx lines used is equal to the
number of processors in the system. Each processor drives the BRx pin that
corresponds to its ID2-0 inputs and monitors all others.
L
If less than four processors are used in the system, the unused BRx
pins should be tied high.
When one of the slave processors needs to become bus master, it automat-
ically initiates the bus arbitration process by asserting its BRx line at the
beginning of the cycle. Later in the same cycle, the processor samples the
value of the other BRx lines.
The cycle in which mastership of the bus is passed from one processor to
another is called a bus transition cycle (BTC). A BTC occurs when the
current bus master’s
BRx pin is deasserted and one or more of the slave’s
BRx pins is asserted. The bus master can retain bus mastership by keeping
its
BRx pin asserted.
By observing all of the
BRx lines, each processor can detect when a bus
transition cycle occurs and which processor has become the new bus mas-
ter. A bus transition cycle is the only time that bus mastership is
transferred.
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