ADSP-21368 SHARC Processor Hardware Reference 7-9
Input Data Port
(bit 26 in the
IDP_PP_CTL register) selects between the two sets of pins that
may be used as the parallel input port. When IDP_PORT_SELECT is set (= 1),
the data bits are read from DATA31–12 and the control signals come from
DATA11-8. When IDP_PORT_SELECT is cleared (= 0), the data bits are read
from DAI_P20–1. When IDP_PORT_SELECT is set to 1, the PDAP can be
operated through data pins alone (data and controls can be completely
routed through the DATA pins).
Masking
The IDP_PP_CTL register provides 20 mask bits that allow the input from
any of the 20 pins to be ignored. The mask is specified by setting the
IDP_Pxx_PDAPMASK bits (bits 19–0 of the IDP_PP_CTL register) for the 20
parallel input signals. For each of the parallel inputs, a bit is set (= 1) to
indicate the bit is unmasked and therefore its data can be passed on to
read, or a bit is masked (= 0) so its data is not read. After this masking pro-
cess, data gets passed along to the packing unit.
Packing Unit
The parallel data acquisition port (PDAP) packing unit receives masked
parallel subwords from the 20 parallel input signals and packs them into a
32-bit word. The IDP_PDAP_PACKING bit field (bits 28–27 of the
IDP_PP_CTL register), indicates how data is to be packed. Data can be
packed in any of four modes. Selection of packing mode is made based on
the application.
Packing Mode 11
Mode 11 provides for 20 bits coming into the packing unit and 32 bits
going out to the FIFO in a single cycle. On every clock edge, 20 bits of
data are moved and placed in a 32-bit register, left-aligned. That is, bit 19
maps to bit 31. The lower bits, 11–0, are always set to zero, as shown in
Figure 7-13.
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