Making Connections in the SRUs
4-60 ADSP-21368 SHARC Processor Hardware Reference
Group C Connections—Pin Enable Signals
Group C signals, shown in Table 4-13 on page 4-62, are used to specify
whether each DPI pin is used as an output or an input by setting the
source for the pin buffer enable. When a pin buffer enable (
DPI_PBENxx_I)
is set (= 1), the signal present at the corresponding pin buffer input
(DPI_PBxx_I) is driven off chip as an output. When a pin buffer enable is
cleared (= 0), the signal present at the corresponding pin buffer input is
ignored.
The registers that control group C settings are shown in Figure 4-50
through Figure 4-52.
L
The TWI output is an open-drain output so the pins used for TWI
data and clock should be connected to logic level 0.
110010 50 PCG_FSD_O Precision clock generator frame sync D out
110011–
111111
51-63 RESERVED
Table 4-12. Group B Signals (Cont’d)
Binary Decimal Signal Description
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