ADSP-21368 SHARC Processor Hardware Reference 6-33
Serial Peripheral Interface Ports
When the SPI port is transmitting, two eight-bit words are unpacked from
one 32-bit word. When receiving, words are packed into one 32-bit word
from two eight-bit words.
An example of unpacking the data before transmitting:
The value
0xXXLMXXJK (where XX is any random value and JK and LM
are the data words to be transmitted out of the SPI port) is written
to the TXSPI register. The processor transmits 0xJK first and then
transmits 0xLM.
An example of packing on the received data (SGN is sign extend data where
1 = sign extend and 0 = no sign extend):
The receiver packs the two words received, 0xJK and then 0xLM,
into a 32-bit word. They appear in the RXSPI register as:
0x00LM00JK => if SGN is configured to 0 or L, J < 7
0xFFLMFFJK => if SGN is configured to 1 and L, J > 7
SPI Interrupts
The SPI ports can generate interrupts in five different situations. During
core-driven transfers, an SPI interrupt is triggered:
1. When the
TXSPI buffer has the capacity to accept another word
from the core.
2. When the
RXSPI buffer contains a valid word to be retrieved by the
core.
The
TIMOD (transfer initiation and interrupt) register determines whether
the interrupt is based on the
TXSPI or RXSPI buffer status. For more infor-
mation, refer to the
TIMOD bit descriptions in the SPICTL register in
Table A-10 on page A-54.
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