Analog Devices SHARC ADSP-21368 User Manual

Configuring IOP/Core Interaction
2-18 ADSP-21368 SHARC Processor Hardware Reference
A TCB chain load request is prioritized like all other DMA operations.
The I/O processor latches a TCB loading request and holds it until the
load request has the highest priority. If multiple chaining requests are
present, the I/O processor services the
TCB registers for the highest priority
DMA channel first. A channel that is in the process of chain loading can-
not be interrupted by a higher priority channel. For a list of DMA
channels in priority order, see Table 2-7 on page 2-32.
Setting Up DMA Channel Allocation and Priorities
There are between 24 and 34 channels of DMA available on the
ADSP-21367/8/9 and ADSP-2137x processors, depending on the proces-
sor model. The maximum number is configured as—16 via the serial
ports, 8 via the input data port, 4 for the UARTs, 2 for the SPI interface,
2 for the external port, and 2 for memory-to-memory transfers. Each
channel has a set of parameter registers which are used to set up DMA
Table 2-4. TCB Chain Loading Sequence
1
Address
2
External Port Serial Ports SPI Port
CPSPx + 0x0008 0000 See Table 2-9, Table 2-10,
Table 2-11
IISPx IISPI
CPSPx – 1 + 0x0008 0000 IMSPx IMSPI
CPSPx – 2 + 0x0008 0000 CSPx CSPI
CPSPx – 3 + 0x0008 0000 CPSPx CPSPI
CPSPx – 4 + 0x0008 0000
CPSPx – 5 + 0x0008 0000
CPSPx – 6 + 0x0008 0000
1 Chaining is not available using the IDP port.
2 An “x” denotes the DMA channel used. While the TCB is eight locations in length, SPI and serial
ports only use the first four locations.

Analog Devices SHARC ADSP-21368 Specifications

General

Architecture	SHARC
Core Processor	ADSP-21368
Core Clock Speed	400 MHz
Serial Ports	1
SPORTs	4
SPI Ports	1
I2C Ports	1
Timers	2
DMA Channels	14
Operating Voltage - Core	1.2 V
Operating Voltage - I/O	3.3 V
Data Bus Width	32-bit
Operating Temperature	-40°C to +85°C
Number of Cores	1
Audio Processing	Yes
Package	LQFP