ADSP-21368 SHARC Processor Hardware Reference 6-1
6 SERIAL PERIPHERAL
INTERFACE PORTS
The ADSP-21367/8/9 and ADSP-2137x processors are equipped with
two synchronous serial peripheral interface ports that are compatible with
the industry-standard serial peripheral interface (SPI). The SPI ports are
routed through the digital peripheral interface pins (DPI14–1). At reset,
SPI functionality is available on DPI pins 1–8. For more information, see
Chapter 4, Digital Audio/Digital Peripheral Interfaces. Each SPI port has
its own unique set of control registers (the secondary register set is differ-
entiated by a B in the register name as in SPIBAUDB). The SPI ports
support communication with a variety of peripheral devices including
CODECs, data converters, sample rate converters, S/PDIF or AES/EBU
digital audio transmitters and receivers, LCDs, shift registers, microcon-
trollers, and FPGA devices with SPI emulation capabilities.
Each SPI port provides the following features and capabilities:
• A simple 4-wire interface consisting of two data pins, a device
select pin, and a clock pin
• Full-duplex operation that allows the processor to transmit and
receive data simultaneously on the same port
• Special data formats to accommodate little and big endian data,
different word lengths, and various packing modes
• Master and slave modes as well as multimaster mode in which the
processors can be connected to four other SPI devices
• Open drain outputs to avoid possible driver damage due to data
contention and to support multimaster scenarios
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