Configuring IOP/Core Interaction
2-20 ADSP-21368 SHARC Processor Hardware Reference
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If a DMA channel is disabled (EPDEN, SPIDEN, SDEN, or IDP_DMA_EN
bits =0), the I/O processor does not issue internal DMA grants to
that channel (whether or not the channel has data to transfer).
The default DMA channel priority is fixed prioritization by DMA channel
group (serial ports, TWI, UART, IDP, or SPI port). Table 2-7 on
page 2-32 lists the DMA channels in descending order of priority.
For information on programming serial port priority modes, see
Table 5-11 on page 5-74.
The I/O processor determines which DMA channel has the highest prior-
ity internal DMA request during every cycle between each data transfer.
Processor core accesses of I/O processor registers and TCB chain loading
(both of which occur after the IOD transfer) are subject to the same prior-
itization scheme as the DMA channels. Applying this scheme uniformly
prevents I/O bus contention, because these accesses are also performed
over the internal I/O bus. For more information, see “Chaining DMA
Processes” on page 2-14.
DMA Bus Arbitration
DMA channel arbitration is the method that the IOP uses to determine
how groups rotate priority with other channels. This feature is enabled by
setting the
DCPR bit in the IOP’s SYSCTL register.
DMA-capable peripherals execute DMA data transfers to and from inter-
nal memory over the IOD bus. When more than one of these peripherals
requests access to the IOD bus in a clock cycle, the bus arbiter, which is
attached to the IOD bus, determines which master should have access to
the bus and grants the bus to that master.
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