Designing for High Frequency Operation
14-34 ADSP-21368 SHARC Processor Hardware Reference
Keep the portions of the system that operate at different frequencies as
physically separate as possible. The clock supplied to the processor must
have a rise time of 3 ns or less and must meet or exceed a high and low
voltage of 2 V and 0.4 V, respectively.
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Never share a clock buffer IC with a signal of a different clock fre-
quency as this introduces excessive jitter.
Other Recommendations and Suggestions
• Use more than one ground plane on the PCB to reduce crosstalk.
Be sure to use lots of vias between the ground planes. One V
DD
plane for each supply is sufficient. These planes should be in the
center of the PCB.
• To reduce crosstalk, keep critical signals such as clocks, strobes,
and bus requests on a signal layer next to a ground plane and away
from these signals, or layout critical signals perpendicular to other
non-critical signals.
• If possible, position the processors on both sides of the board to
reduce area and distances.
• To allow better control of impedance and delay, and to reduce
crosstalk, design for lower transmission line impedances.
• Use 3.3 V peripheral components and power supplies to help
reduce transmission line problems, ground bounce and noise cou-
pling (the receiver switching voltage of 1.5 V is close to the middle
of the voltage swing).
• Experiment with the board and isolate crosstalk and noise issues
from reflection issues. This can be done by driving a signal wire
from a pulse generator and studying the reflections while other
components and signals are passive.
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