Analog Devices SHARC ADSP-21368 User Manual

ADSP-21368 SHARC Processor Hardware Reference 14-51
System Design
Following that, a 24-bit address (all zeros) is always driven by the proces-
sor. On the following
SPICLK cycle (cycle 32), the processor expects the
first bit of the first word of the boot stream. This transfer continues until
the kernel has finished loading the user program into the processor.
Booting From an SPI Flash
For SPI flash devices, the format of the boot stream is identical to that
used in SPI slave mode, with the first byte of the boot stream being the
first byte of the kernel. This is because SPI flash devices do not drive out
data until they receive an 8-bit command and a 24-bit address.
Figure 14-16. SPI Master Mode Booting Using Various Serial Devices
0X000X03 0X00 0X00
1ST KERNEL
BY TE
0X00
1ST KERNEL
BYTE
SPI FLASH DRIVES DATA AFTER IT
RE CE IVE S TH E 8 -BI T RE AD CO MM A ND
AND A 24-BIT ADDRESS
SPI EEPROMS DRIVE DATA AFTER
RECEIVING THE 8-BIT READ COMMAND
AND A 1 6-BI T AD D R ES S
SPI SLAV E
FLASH
(2 4-BI T ADDR ES S)
SPI SLAV E
EEPROM
(1 6-BI T ADDR ES S)
SPI SLAV E
HOST
(NO COMMAND)
LOADER PADS ONE DUMMY BYTE
TO THE BOOT STREAM OF
HOST SPIDEVICES
SPI HOST DRIVES DATA
THROUGHOUT THE 8-BIT READ
COMMAND AND 24-BIT ADDRESS
0X000X00 0X00 0X00
1ST KERNEL
BYTE
LOADER PADS FOUR DUMMY
BYTES TO THE BOOT
STREAM OF HOST SPI DEVICES
SPICLK
DRIVEN BY MASTER
MASTER OUT
SLAVEIN
(M OS I)
MASTER IN
SLAVE OUT
(MISO)
t=0
t=32 SPICLK

Analog Devices SHARC ADSP-21368 Specifications

General

Brand	Analog Devices
Model	SHARC ADSP-21368
Category	Computer Hardware
Language	English