ADSP-21368 SHARC Processor Hardware Reference 5-1
5 SERIAL PORTS
The ADSP-21367/8/9 and ADSP-2137x processors have up to eight inde-
pendent, synchronous serial ports (SPORTs) that provide an I/O interface
to a wide variety of peripheral devices. They are called SPORT0,
SPORT1, SPORT2, SPORT3, SPORT4, SPORT 5, SPORT6, and
SPORT7. Each SPORT has its own set of control registers and data buff-
ers. With a range of clock and frame synchronization options, the
SPORTs allow a variety of serial communication protocols and provide a
glueless hardware interface to many industry-standard data converters and
CODECs.
Serial ports can operate at one-eighth the full clock rate of the processor, a
maximum rate of 50M bit/s for (CCLK) = 3 ns. If channels A and B are
active, each SPORT has 83.3M bit/s maximum total throughput. Bidirec-
tional (transmit or receive) functions provide greater flexibility for serial
communications. Serial port data can be automatically transferred to and
from on-chip memory using DMA block transfers. In addition to standard
synchronous serial mode, each SPORT offers a time division multiplexed
(TDM) multichannel mode, left-justified sample pair mode, and I
2
S
mode.
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