ADSP-21368 SHARC Processor Hardware Reference 4-67
Digital Audio/Digital Peripheral Interfaces
Just as the core has its own interrupt latch registers (
IRPTL and LIRPTL),
the DAI has its own latch registers (DAI_IRPTL_L and DAI_IRPTL_H). When
a DAI interrupt is configured to be high priority, it is latched in the
DAI_IRPTL_H register. When any bit in the DAI_IRPTL_H register is set
(= 1), bit 11 in the IRPTL register is also set and the core services that
interrupt with high priority. When a DAI interrupt is configured to be
low priority, it is latched in the DAI_IRPTL_L register. Similarly, when any
bit in the DAI_IRPTL_L register is set (= 1), bit 6 in the LIRPTL register is
also set and the core services that interrupt with low priority. Regardless of
the priority, when a DAI interrupt is latched and promoted to the core
interrupt latch, the ISR must query the DAI’s interrupt controller to
determine the source(s). Sources can be any one or more of the interrupt
controller’s 32 configurable channels (DAI_INT31–0). For more informa-
tion, see “DAI Interrupt Controller Registers” on page A-112.
L
Reading the DAI’s interrupt latches clears them. Therefore, the
ISR must service all the interrupt sources it discovers. That is, if
multiple interrupts are latched in one of the DAI_IRPTL_x registers,
all of them must be serviced before executing an RTI instruction.
The IDP_FIFO_GTN_INT interrupt is not cleared when the DAI_IRPTL_H/L
registers are read. This interrupt is cleared automatically when the situa-
tion that caused the interrupt goes away.
DPI Interrupts
The DPI also has an interrupt controller, similar to that in the DAI. There
are 14 interrupts—4 from the UARTs, 1 from the two wire interface
(TWI) and 9 general-purpose I/O interrupts. All of these interrupts are
combined into a single interrupt, namely DPI_INT. The DPI_IRPTL register
contains the status on individual interrupts. Apart from
DPI_IRPTL, there
are two additional registers, DPI_IRPTL_RE and DPI_IRPTL_FE which are
used for interrupt latching. Setting a corresponding bit in the
DPI_IRPTL_RE
register enables interrupt latching at the rising edge of the
corresponding signal. Similarly, setting a corresponding bit in the
To Next Page
Loading...
Need help?
General
