DAI/DPI Interrupt Controller
4-68 ADSP-21368 SHARC Processor Hardware Reference
DPI_IRPTL_FE register enables interrupt latching at the falling edge of that
signal. A particular interrupt can be latched at the rising or falling edge
independently. Keeping corresponding bits reset in both these registers
(DPI_IRPTL_RE and DPI_IRPTL_FE) disables the corresponding interrupt.
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The DPI_INT interrupt is automatically cleared when the DPI_IRPTL
register is read for the EXT_MISC, UART_TX, and UART_RX (for DMA
mode only) interrupts. Furthermore, the UART_RX interrupt for I/O
mode must be cleared in the ISR. For information on using inter-
rupts in the UART, see “UARTxIER Register” on page 11-7, and
“UARTxIIR Register” on page 11-9. For information on using
interrupts in the TWI, see “Interrupt Source Register” on
page 12-7 and “Interrupt Enable Register” on page 12-8.
The UART and TWI interrupts are only used as rising edge interrupts.
The corresponding bits in the DPI_IRPTL_FE register are reserved. By
default, at reset, all interrupts are disabled (in other words, both the
DPI_IRPTL_RE and DPI_IRPTL_FE registers have zero values).
Interrupt service routines (ISR) must read the DPI_IRPTL register to dis-
cover all of the interrupts that are currently latched. A shadow register,
DPI_IRPTL_SH, is provided for the primary register DPI_IRPTL. Reads of
this register returns data in the DPI_IRPTL register without clearing the
contents of the register.
Note that the ISR must make sure that the current interrupt condition is
removed before exiting to the main program. Further note that for the
interrupts corresponding to the UART and the TWI, the bits in the
DPI_IRPTL_RE register are used as enable bits and corresponding bits from
the DPI_IRPTL_FE register are not used.
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