ADSP-21368 SHARC Processor Hardware Reference 10-13
Asynchronous Sample Rate Converter
Enabling the SRC
When the SRCx_ENABLE bit (bit 31 in the SRC control registers) is set
(= 1), the SRC begins its initialization routine where all locations in the
FIFO are initialized to zero, MUTE_OUT is cleared, and any output pins are
enabled.
The SRCx_ENABLE bit should be held low for a minimum of five PCLK cycles
when setting or clearing the bit. It is recommended that the SRC be dis-
abled when changing modes.
When the SRCx_ENABLE bit is set or there is a change in the sample rate
between LRCLK_I and LRCLK_O, the MUTE_OUT pin is cleared. The MUTE_OUT
pin remains cleared until the digital-servo loop’s internal fast settling
mode is complete. When the digital-servo loop has switched to slow set-
tling mode, the MUTE_OUT pin is set. While MUTE_OUT is cleared, the
MUTE_IN pin should be cleared as well to prevent any major distortion in
the audio output samples.
Serial Data Ports
The serial data ports provide the interface through which data is trans-
ferred into and out of the SRC modules. The following sections describe
the various data formats and the available modes of operation.
Data Format
The serial data input port mode is set by the logic levels on the
SRCx_SMODEIN[0:2] bits that are located in the SRCCTLx registers. The
serial data input port modes available are left-justified, I
2
S, TDM and
right-justified, 16, 18, 20, or 24 bits as defined in Table 10-1.
The serial data output port mode is set by the logic levels on the
SRCx_SMODE_OUT[0:1] bits. The serial mode can be changed to left-justi-
fied, I
2
S, right-justified, or TDM as defined in Table 10-2. The output
word width can be set by using the
SRCx_LENOUT[0:1] bits as shown in
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